DMA transfer is known as a method of directly transferring data between a memory and another device not by way of a CPU. Generally a DMA transfer has the advantage in a large volume data transfer compared with a PIO (Programmed I/O) transfer by way of a CPU, since burst transfer is possible and the load applied to the CPU can be distributed. Also in order to support a format of creating one data packet by chaining a plurality of segments, such as the case of Ethernet, DMAC (Direct Memory Access Controller: DMA controller) for controlling DMA transfer generally has a chain mode for continuously transferring a plurality of data segments at the transfer source, in addition to a single transmission mode for transferring one data segment at the transfer source.
In this chain mode, it is effective if an arbitrary address is allowed to locate the data segment at the transfer source, in terms of flexibility of user programming.
However in DMAC, which is connected to a bus that has a 2-byte or more width, misalignment, that is a status in which the boundary of the burst transfer does not match the bus width, occurs if a plurality of data segments divided at an arbitrary address boundary in byte units are transferred in the chain mode. For example, let us assume the case when the I/O is an Ethernet network adapter. The packet to be transferred from the memory to the I/O is comprised of a plurality of parts, including a header section and a payload section. Generally these parts are often prepared in the work area of each individual memory, and it is necessary to reassemble the individually stored parts and to convert them into a packet format that the I/O can recognize. One means is using DMA transfer, but if an individual part is constructed in an arbitrary address, data in an address that is not aligned to the bus width cannot be burst-transferred.
Therefore a burst transfer which occupies the bus continuously and a partial transfer which transfers data less than the bus width must be combined. In this case, arbitration of the bus enters at the boundary of the transfer, so the bus utilization efficiency drops compared to the case of all data being burst-transferred.
Examples of a DMA control method for handling such a misalignment problem are Japanese Patent Application Laid-Open Nos. H5-67035, H9-146877 and 2000-132497. The method shown in Japanese Patent Application Laid-Open No. H5-67035 is not preferable in terms of load distribution on the CPU, since alignment is adjusted by CPU control. Japanese Patent Application Laid-Open Nos. H9-146877 and 2000-132497 do not refer to transfer in the chain mode, therefore a drop in bus overhead when misalignment occurs in the chain mode is inevitable.
Also when the transfer destination memory, which is the destination of data transfer, is cache-controlled, an unnecessary cache control operation may be generated if burst-transfer is performed at an arbitrary address boundary for each received packet.
To solve these problems, it is an object of the present invention to provide a DMA controller, DMA control method and DMA control program to avoid dropping bus utilization efficiency when data segments, divided at arbitrary address boundaries in byte units, are DMA-transferred in the chain mode.